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P4C165 ULTRA HIGH SPEED 8K x 8 RESETTABLE STATIC CMOS RAM
FEATURES
Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times) - 15/20/25 ns (Commercial) - 20/25/35 (Industrial) Low Power Operation Chip Clear Function Output Enable and Dual Chip Enable Control Functions Single 5V10% Power Supply Common Data I/O Fully TTL Compatible Inputs and Outputs Standard Pinout (JEDEC Approved) - 28-Pin Plastic DIP (300 mil)
DESCRIPTION
The P4C165 is a 65,536-bit ultra high-speed static RAM organized as 8K x 8. The RAM features a reset control to enable clearing all words to zero within two cycle times. The CMOS memory requires no clocks or refreshing and has equal access and cycle times. Inputs are fully TTLcompatible. The RAM operates from a single 5V10% tolerance power supply. Access times as fast as 15 nanoseconds are available, permitting greatly enhanced system operating speeds. In full standby mode with CMOS inputs, power consumption is only 5.5 mW for the P4C165. The P4C165 is available in a 28-pin 300 mil DIP.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
1519B
DIP (P5)
Document # SRAM117 Rev OR 1 Revised October 2005
P4C165
MAXIMUM RATINGS(1)
Symbol VCC Parameter Power Supply Pin with Respect to GND Terminal Voltage with Respect to GND (up to 7.0V) Operating Temperature Value -0.5 to +7 -0.5 to VCC +0.5 -55 to +125 Unit V Symbol TBIAS TSTG PT IOUT Parameter Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Value -55 to +125 -65 to +150 1.0 50 Unit C C W mA
VTERM TA
V C
RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE
Grade(2) Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C GND 0V 0V VCC 5.0V 10% 5.0V 10%
CAPACITANCES(4)
VCC = 5.0V, TA = 25C, f = 1.0MHz Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions Typ. Unit VIN = 0V VOUT = 0V 5 7 pF pF
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage(2) Symbol VIH VIL V HC VLC V CD VOL VOH ILI ILO ISB Parameter Input High Voltage Input Low Voltage CMOS Input High Voltage CMOS Input Low Voltage Input Clamp Diode Voltage Output Low Voltage (TTL Load) Output High Voltage (TTL Load) Input Leakage Current Output Leakage Current Standby Power Supply Current (TTL Input Levels) Standby Power Supply Current (CMOS Input Levels) VCC = Min., IIN = -18 mA IOL = +8 mA, VCC = Min. IOH = -4 mA, VCC = Min. VCC = Max. VIN = GND to VCC VCC = Max., CE = VIH, VOUT = GND to VCC CE VIH or CE2 VIL, VCC= Max f = Max., Outputs Open CE VHC or CE2 VLC, VCC= Max f = 0, Outputs Open VIN VLC or VIN VHC Ind./Com'l. Ind./Com'l. -5 ___ +5 30 A mA Ind./Com'l. -5 +5 A 2.4 Test Conditions P4C165 Min Max 2.2 -0.5(3) -0.5
(3)
Unit V V V V V V V
VCC +0.5 0.8 0.2 -1.2 0.4
VCC -0.2 VCC +0.5
ISB1
Ind./Com'l.
___
15
mA
n/a = Not Applicable Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability. 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with VIL and IIL not more negative than -3.0V and -100mA, respectively, are permissible for pulse widths up to 20 ns. 4. This parameter is sampled and not 100% tested.
Document # SRAM117 Rev OR
2
Page 2 of 9
P4C165
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol ICC Parameter Dynamic Operating Current* Temperature Range Commercial Industrial -15 160 N/A -20 155 160 -25 150 155 -35 N/A 150 Unit mA mA
*VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE1 = VIL, CE2 = VIH, OE = VIH
AC ELECTRICAL CHARACTERISTICS--READ CYCLE
(VCC = 5V 10%, All Temperature Ranges)(2)
Sym. t RC tAA tAC t OH tLZ t HZ tOE
Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Hold from Address Change Chip Enable to Output in Low Z Chip Disable to Output in High Z Output Enable Low to Data Valid
-15 15 15 15 3 2 8 9 2 9 0 15 0 2 3 2
-20 20 20 20 3 2 8 10 2 9 0 20
-25 25 25 25 3 2 10 13 2 12 0 20
-35 35 35 35
Min Max Min Max Min Max Min Max
Unit ns ns ns ns ns ns ns ns ns ns
15 18 15
tOLZ Output Enable Low to Low Z tOHZ Output Enable High to High Z t PU t PD Chip Enable to Power Up Time Chip Disable to Power Down Time
20
ns
Document # SRAM117 Rev OR
3
Page 3 of 9
P4C165
READ CYCLE NO. 1 (OE CONTROLLED)(5) OE
READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6)
READ CYCLE NO. 3 (CE1, CE2 CONTROLLED)(5,7,10) CE
Notes: 5. WE is HIGH for READ cycle. 6. CE1 is LOW, CE2 is HIGH and OE is LOW for READ cycle. 7. ADDRESS must be valid prior to, or coincident with CE1 transition LOW and CE2 transition HIGH. 8. Transition is measured 200 mV from steady state voltage prior to change, with loading as specified in Figure 1. This parameter is sampled and not 100% tested.
9. READ Cycle Time is measured from the last valid address to the first transitioning address. 10. Transitions caused by a chip enable control have similar delays irrespective of whether CE1 or CE2 causes them.
Document # SRAM117 Rev OR
4
Page 4 of 9
P4C165
AC CHARACTERISTICS--WRITE CYCLE
(VCC = 5V 10%, All Temperature Ranges)(2)
Sym. tWC tCW tAW tAS tWP tAH tDW tDH tWZ tOW
Parameter Write Cycle Time Chip Enable Time to End of Write Address Valid to End of Write Address Set-up Time Write Pulse Width Address Hold Time Data Valid to End of Write Date Hold Time Write Enable to Output in High Z Output Active from End of Write
-15 15 12 12 0 12 0 9 0 7 3 3
-20 20 15 15 0 15 0 11 0 8 3
-25 25 18 18 0 18 0 13 0 10 3
-35 35 25 25 0 20 0 15 0 14
Min Max Min Max Min Max Min Max
Unit ns ns ns ns ns ns ns ns ns ns
WRITE CYCLE NO. 1 (WE CONTROLLED)(11) WE
Notes: 11. CE1 and WE must be LOW, and CE2 HIGH for WRITE cycle. 12. OE is LOW for this WRITE cycle to show tWZ and tOW. 13. If CE1 goes HIGH, or CE2 goes LOW, simultaneously with WE HIGH, the output remains in a high impedance state.
14. Write Cycle Time is measured from the last valid address to the first transitioning address.
Document # SRAM117 Rev OR
5
Page 5 of 9
P4C165
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CONTROLLED)(11) CE
AC CHARACTERISTICS--CLEAR CYCLE
(VCC = 5V 10%, All Temperature Ranges)(2)
Sym. tCLCL tCLIX tCLIR
Parameter CLEAR Cycle Time CLEAR Low to Inputs Don't Care CLEAR Low to Inputs Recognized
-15 30 12 0 30
-20 40 15 0 40
-25 50 15 0 50
-35 70 20 0 70
Min Max Min Max Min Max Min Max
Unit ns ns ns ns
tCLPW CLEAR Pulse Width
TIMING WAVEFORM OF CLEAR CYCLE
Document # SRAM117 Rev OR
6
Page 6 of 9
P4C165
AC TEST CONDITIONS
Input Pulse Levels Input Rise and Fall Times Input Timing Reference Level Output Timing Reference Level Output Load 1.5V See Figures 1 and 2 1.5V 3ns GND to 3.0V
TRUTH TABLE
Mode Reset Standby Standby Output Disabled Read Write CLEAR CE1 L H H H H H X H X L L L CE2 X X L H H H OE X X X H L X WE X X X H H L I/O --High Z High Z High Z DOUT High Z Power Active Standby Standby Active Active Active
Figure 1. Output Load
* including scope and test fixture. Note: Because of the ultra-high speed of the P4C165, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 F high frequency capacitor is also required between VCC and ground. To avoid signal
Figure 2. Thevenin Equivalent
reflections, proper termination must be used; for example, a 50 test environment should be terminated into a 50 load with 1.73V (Thevenin Voltage) at the comparator input, and a 116 resistor must be used in series with DOUT to match 166 (Thevenin Resistance).
Document # SRAM117 Rev OR
7
Page 7 of 9
P4C165
ORDERING INFORMATION
SELECTION GUIDE
The P4C165 is available in the following temperature, speed and package options.
Temperature Range Commercial Industrial Package Plastic DIP Plastic DIP Speed 15 -15PC -15PI 20 -20PC -20PI 25 -25PC -25PI 35 -35PC -35PI
Pkg # # Pins Symbol A A1 b b2 C D E1 E e eB L
P5
28 (300 mil) Min Max 0.210 0.014 0.023 0.045 0.070 0.008 0.014 1.345 1.400 0.270 0.300 0.300 0.380 0.100 BSC 0.430 0.115 0.150 0 15
PLASTIC DUAL IN-LINE PACKAGE
Document # SRAM117 Rev OR
8
Page 8 of 9
P4C165
REVISIONS
DOCUMENT NUMBER: DOCUMENT TITLE: REV. OR ISSUE DATE Oct-05 SRAM117
P4C165 ULTRA HIGH SPEED 8K x 8 RESETTABLE STATIC CMOS RAM
ORIG. OF CHANGE JDB
DESCRIPTION OF CHANGE New Data Sheet
Document # SRAM117 Rev OR
9
Page 9 of 9

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